1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for forming a suicide layer of a semiconductor device in which a DRAM and a logic circuit are merged.
2. Description of the Related Art
Silicide is an alloy of silicon and a metal, formed by stacking a refractory metal or a transition metal on polysilicon, and annealing the resultant structure. Silicide has been used recently for electrodes and interconnections of semiconductor devices. This is because silicide can provide low resistance which is not possible using polysilicon. Thus, when a silicide layer is formed on a gate electrode and source and drain areas of a MOS transistor, the interconnection material has low resistance, allowing the semiconductor device to operate at high speed.
The technology for forming silicide has been applied to various memory devices, logic devices or bipolar devices. In order to realize high speed operation of a dynamic random access memory (DRAM) and metal oxide semiconductor (MOS) transistors such as in a merged DRAM logic, a selective silicide layer must be formed only on gate electrodes in a predetermined area of the MOS transistors, but the silicide layer must be concurrently formed on the source and drain areas as well as the gate electrodes in other areas of the merged DRAM logic. Here, by typical photo etching, when the insulating layer formed on the gate electrode of the MOS transistor is patterned to expose the gate electrode, misalignment occurs, causing the gate electrode not to be exposed, or the source and drain areas adjacent to the gate electrode to be exposed to form a silicide layer.
Thus, the silicide layer must be selectively formed only on the gate electrodes in a predetermined area of the MOS transistors, and concurrently formed in the source and drain areas as well as the gate electrodes in other areas of the merged DRAM logic.